GHEVC: GPU-based HEVC decoder

Speaker:  Leonel Sousa – INESC-ID, Rua Alves Redol, 9, Portugal
Topic(s):  Architecture, Embedded Systems and Electronics, Robotics


For High-Efficiency Video Coding (HEVC) decoders, a significant increase of the computational load is a limiting factor to accomplish real-time, especially for high definition video sequences (e.g. Ultra HD 4K and beyond). Modern Graphics Processor Units (GPUs) have evolved into programmable and powerful parallel accelerators, being able to deliver an execution performance that significantly exceeds the capabilities of multi-core Central Processing Units (CPUs). However, this performance is mostly attainable for compute-intensive applications, with a significant amount of data parallelism and regular memory access patterns. Accordingly, fully exploiting the GPU capabilities for a set of different and computationally complex HEVC decoding procedures is a challenge that this tutorial addresses by presenting an efficient GPU-based HEVC decoder, denoted as GHEVC. Such a data-parallel GHEVC decoder integrates the whole decompression pipeline, where the several HEVC procedures are executed in a highly heterogeneous environment composed by a CPU and a GPU. The developed algorithms comprehensively exploit both coarse and fine-grained parallelization opportunities in an integrated perspective by re-designing the execution pattern of the involved HEVC procedures, while simultaneously coping with their inherent computational complexity and data dependencies. As a result, the GHEVC decoder, which is fully compliant with the HEVC standard, has shown to be a remarkable approach, being capable of satisfying hard real-time requirements to process Ultra HD video sequences.

About this Lecture

Number of Slides:  60
Duration:  60 minutes
Languages Available:  English
Last Updated: 

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