Timing Aware High Level Synthesis for Efficient Digital system building

The timing closure problem is one of the most important problems in the design automation. However, the rapid increase of the impact of the process variation on circuit timing makes the problem much more complicated and unpredictable to tackle in synthesis. Process variations are of great concern in deep submicron technology. Early prediction of their effects on the circuit performance and parametric yield is extremely useful. Due to the increase of the design complexity in today's SoC chips, a demand for high level synthesis, prediction and timing analysis has increased. 

The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forced design methodologies and tools to move to higher abstraction levels. Raising the abstraction levels and accelerating automation of both the synthesis and the verification processes.

The logic synthesis application automatically converted the RTL representation into a mixture of registers and Boolean equations, performed a variety of minimizations and optimizations (including optimizing for area and timing), and then generated a gate-level netlist that would (or at least, should) meet the original timing constraints High-level synthesis is an automated method of creating RTL designs from algorithmic descriptions.

Static Timing Analysis (STA) is one of the techniques to verify design in terms of timing. This kind of analysis doesn’t depend on any data or logic inputs, applied at the input pins. The input to an STA tool is the routed netlist, clock definitions (or clock frequency) and external environment definitions. The STA will validate whether the design could operate at the rated clock frequency, without any timing violations. This discussion focus on efficient digital system design with high level synthesis and timing closure analysis.