Exploiting eDRAM bandwidth with data prefetching: simulation and

Speaker:  Valentina Salapura – NY, United States
Topic(s):  Architecture, Embedded Systems and Electronics, Robotics

Abstract

Compared to conventional SRAM, embedded DRAM (eDRAM) offers power, bandwidth and density advantages for large on-chip cache memories. However, eDRAM suffers from comparatively slower access times than conventional SRAM arrays. To hide eDRAM access latencies, the Blue Gene/L supercomputer implements small private prefetch caches.

            We present an exploration of design trade-offs for the prefetch D-cache for eDRAM. We use full system simulation to consider operating system impact. We validate our modeling environment by comparing our simulation results to measurements on actual Blue Gene systems. Actual execution times also include any system effects not modeled in our performance simulator, and confirm the selection of simulation parameters included in the model.

            Our experiments show that even small prefetch caches with wide lines efficiently capture spatial locality in many applications. We find that a 2kB private prefetch caches reduce execution time by 10% on average, effectively hiding the latency of the eDRAM-based memory system.

About this Lecture

Number of Slides:  na
Duration:  60 minutes
Languages Available:  English
Last Updated: 

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