Nanoscale Interconnect Optimizations for Emerging TechnologiesSpeaker: Shiyan Hu – Southampton, United Kingdom
Topic(s): Graphics and Computer-Aided Design
AbstractAs the VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Interconnect synthesis which includes buffer insertion and layer assignment is indispensable in the physical synthesis flow. In this talk, I will first introduce the classical dynamic programming based buffer insertion and layer assignment techniques. I will then highlight our recent work on developing a new provably good algorithm for the timing driven minimum cost buffer insertion problem. This NP-hard problem has been studied for over a decade but there is little success in designing efficient approximations. Our algorithm is the first fully polynomial time approximation scheme which can approximate the optimal solution within a factor of 1+e running in O(m2n2b/e3+n3b2/e) time for any 0<e<1. I will then show how this algorithm can be extended to handle layer assignment. Finally, I will briefly describe our recently developed buffer insertion technique for the carbon nanotube interconnect based IC design, which is the first buffering technique in this emerging research area.
About this LectureNumber of Slides: 68
Duration: 60 minutes
Languages Available: Chinese (Simplified), English
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