Post-Silicon Validation and Debug

Speaker:  Prabhat Mishra – Gainesville, FL, United States
Topic(s):  Graphics and Computer-Aided Design

Abstract

Post-silicon validation is widely acknowledged as a major bottleneck for complex integrated circuits. Due to increasing design complexity coupled with shrinking time-to-market constraints, it is not possible to detect all design flaws (errors) during pre-silicon validation. Post-silicon validation needs to capture these escaped functional errors as well as electrical faults. A major concern during post-silicon debug is the limited observability and controllability of internal signals. In this talk, I will primarily focus on three related research challenges: i) restoration-aware trace signal selection, ii) observability-aware directed test generation techniques, and iii) high-level debug to reproduce post-silicon failures. I will highlight promising signal selection methods that can select profitable signals to maximize observability. Next, I will describe automated test generation techniques that are aware of the selected signals such that the generated tests are debug friendly. Finally, I will discuss high-level debug framework for analyzing post-silicon failures. Observability-aware test generation coupled with effective utilization of on-chip debug structures is expected to significantly reduce the overall post-silicon debug complexity.

About this Lecture

Number of Slides:  90
Duration:  60 minutes
Languages Available:  English
Last Updated: 

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