Dynamic Legacy Code Migration Through Binary-Synthesis on Heterogeneous Multiprocessor on Chips

Speaker:  Christophe Bobda – Gainesville, FL, United States
Topic(s):  Applied Computing

Abstract

The constant improvement in chip and processor technology poses a major challenge to organizations with enterprise-class legacy software, which need to be run on constantly evolving architectures to leverage their performance improvements.
Legacy code migration can be done in a semiautomatic environment, which involves reverse engineering, business reengineering, schema mapping and translation, data transformation, application development, human computer interaction, and testing. This approach is, however, expensive, challenging and prone to error. Besides large investments in money and human effort required for retargeting a new platform, legacy systems are very brittle with respect to change. Small modifications or enhancements can lead to unexpected system failures which are very difficult to trace in a largely undocumented environment. It is therefore not surprising that of the currently available, and generally ad-hoc methods for legacy system migration, few have had only limited success. As alternative to manual translation, binary translation allows code developed for one instruction set architecture (ISA) to be run on a different ISA without recompilation and without user intervention. Dynamic Binary Translation (DBT) performs this process at run-time by profiling and optimally recompiling frequent executed code blocks for future execution. Dynamic binary translation is well understood for single processors and many mature tools such as virtual machines and just in time compilers rely on DBT in commercialized systems.
The main problem with current binary translators is that they are designed for single processor systems. Extension of those translators to handle multiprocessors is limited to homogenous multi processors by simply duplicating the same translation process for the number of available processors.
Multiprocessor systems today integrate several computing paradigms such as general purpose processors, graphic processors, reconfigurable processors, vector processors and SMID extension, either on a single chip or in desktop or cluster computers. Since applications usually consist of several parts, each of which would benefit more from a certain kind of specialization, this trend is likely to continue in the future. To take advantage of new and future available heterogeneous multiprocessors, a new generation of dynamic binary translators, capable of handling task-level parallelism at run-time, as well as hardware specialization is needed. In this talk, we will discuss the main challenge of online mapping of binary code to heterogeneous multiprocessor architectures, particularly those which incorporate reconfigurable processors. Besides online synthesis of binary code, the talk will focus on virtualizing coarse-grained computing infrastructure on reconfigurable parts to allow for fast synthesis of superblocks at run-time without performance penalty. 

About this Lecture

Number of Slides:  29
Duration:  30 minutes
Languages Available:  English
Last Updated: 

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