System-Level Design of System-on-Chip-Based Embedded Smart Cameras

Speaker:  Christophe Bobda – Gainesville, FL, United States
Topic(s):  Applied Computing


The use of cameras has become a promising alternative to conventional range sensors due to their advantages in size, cost, and accuracy. In many applications, particularly in camera sensor networks, the high-speed requirements along with low-power, size and low-costs are best served with modern system-on-chip devices. They provide a hardware/software structure in which low-level, time consuming, data intensive, and repetitive functions are computed in hardware, while the high-level reasoning is done in software. The hardware parts of the system are usually designed by experienced hardware engineers, using hardware description languages like VHDL. The integration of the hardware and software is classically done at the end of the design process. This approach is error-prone, due to either incorrect specifications or misunderstanding during the translation from high-level specifications to low-level implementation. Consequently, there is a need for a seamless design environment that would allow experts in the fields of artificial intelligence and image processing to focus on the development of intelligent applications that could automatically be mapped to efficient computing platforms. 
In this talk, we present an integrated environment that would help solve this problem and provide designers of image processing systems the proper tools to implement, verify, and evaluate their systems in a real environment.  Our focus is on building a generic embedded hardware/software architecture and providing the symbolic representation to allow programmability at a very high abstraction level. We present a four-level flow, starting from a specification in C/C++ using the OpenCV library. Applications are then partitioned at a transaction-level and captured by a combination of OpenCV and SystemC representation. Subsequent refinements with a hardware design language will produce a hardware implementation at the register transfer level, which will then be simulated, verified synthesized and emulated in a FPGA-based computing infrastructure.

About this Lecture

Number of Slides:  43
Duration:  45 minutes
Languages Available:  English
Last Updated: 

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