Task Scheduling and Hardware Design in Reconfigurable SpaceSpeaker: Amlan Chakrabarti – Kolkata, India
Topic(s): Architecture, Embedded Systems and Electronics, Robotics
Reconfigurable systems are increasingly being employed in a large class of today’s heterogeneous real-time embedded systems which often demand satisfaction of stringent timeliness constraints. However, executing a set of hard real-time applications on reconfigurable systems such that all timing constraints are satisfied while also allowing efficient resource utilization requires effective scheduling, mapping and admission control strategies. In case of hardware tasks the reconfigurable space can considered as partitioned into tiles, which can be mapped to the tasks based on logic requirement and execution deadline. The tradeoff between task throughput, resource and energy requirements can be suitably handled in the run time by considering suitable hardware variants of the tasks that can be mapped through full/partial reconfiguration.
This lecture will brief on the preliminary concepts of embedded task processing on FPGAs using hardware cores and the related architectural design. Scheduling strategies will also be introduced in regards to efficient mapping of hardware tasks on reconfigurable cores both in full and partial reconfiguration domain. A case study on design and implementation of a high speed network security processor (NSP) for SSL,TLS protocol implemented on a system on chip (SOC) will be also be discussed.
About this LectureNumber of Slides: 60
Duration: 120 minutes
Languages Available: English
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