Leonel Sousa received the Ph.D. degree in electrical and computer engineering from the Instituto Superior Técnico (IST), Universidade de Lisboa (UL), Lisbon, Portugal, in 1996. He is currently a Full Professor and Chair of the Electrical and Computer Engineering Department at the IST and a Senior Researcher with the INESC-ID, an R&D Institute owned by IST, Lisbon, Portugal. Prof. Sousa spent two months in Japan at the beginning of 2016 with a prestigious JSPS Invitation Fellowship for Research, and he has been a Visitant Professor of The Carnegie Mellon University (CM) in the fall semester of 2016/2017. As a professor, he has lectured several undergraduate and graduate courses, in the area of computer architecture, embedded systems and digital systems design and supervised 15 Ph.D. Theses. His research interests include high performance computing, computer architectures, computer arithmetic and multimedia systems. He had offered more than 30 keynotes, invited talks and tutorials, he has authored or co-authored more than 250 papers appearing in international journals and conferences and edited five special issues of international journals. He served in the organization of several international conferences and he is an Associate Editor of the IEEE Transactions on Multimedia, IEEE Transactions on Circuits and Systems for Video Technology, IEEE Access, Springer Journal of Real-Time Image Processing, IET Electronics Letters, and he is Editor-in-Chief of the Springer Journal on Embedded Systems. He was the recipient of several awards, including the DASIP’13 Best Paper Award, the SAMOS’11 “Stamatis Vassiliadis” Best Paper Award, the DASIP’10 Best Poster Award, and several Honorable Mention Awards from the Universidade Técnica de Lisboa/Santander Totta (2007, 2009) and the Universidade de Lisboa/Santander (2016) for the quality and impact of his scientific publications. Prof. Sousa is a member of the Management Committee, and leader of the Working Group 1, of EU COST Action NESUS, member of the IFIP WG10.3 on concurrent systems, Senior Member of IEEE, Fellow of the IET, and a Distinguished Scientist of the ACM.
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Cache-Aware Roofline Model: Performance, Power and Energy-Efficiency Limits of Multi-cores
In this talk, a set of fundamental Cache-aware Roofline Models (CARMs) are presented, which describe the performance, power, energy and energy-efficiency upper-bounds of parallel architectures, namely...
GHEVC: GPU-based HEVC decoder
For High-Efficiency Video Coding (HEVC) decoders, a significant increase of the computational load is a limiting factor to accomplish real-time, especially for high definition video sequences (e.g....
Microprocessors, Microcontroller Units and the Internet of Things
Internet of Things (IoT) refers to scenarios where different machines, such as objects, sensors and everyday items, are connected and require minimal human intervention – machine-to-machine interface...
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