Addressing Challenges in Core Microarchitecture Research

Core microarchitecture research is the study of how to implement an Instruction Set Architecture for a general-purpose processor. The field has been studied for decades, but remains crucial due to the evolving demands of modern computing workloads. Growing instruction footprints, the influx of massive data into the processor, the overhead of modern programming languages, and the emphasis on productivity over performance all require innovative approaches. As Moore's Law reaches its end, the onus of improving performance and efficiency falls on microarchitecture research. Additionally, with more and more companies opting to design their own processors, academia is tasked not only with developing new processing technologies but also training the workforce to design these new chips.

In this talk, I will motivate the need for continued core microarchitecture research, give some recent examples of topics we study such as instruction fetch, address translation, and cache management, and give some insight into the challenges we face in this kind of work. For example, branch prediction has been a well-studied topic for decades, but recent trends in software design have caused huge growth in instruction footprints, putting pressure on other areas of instruction fetch as well as overwhelming the capacity of modern branch predictors and ultimately leading to performance degradation.  We demonstrate a practical solution for this problem. I will go deep into a couple of microarchitecture research projects and describe the impact our work has had on thought in industry and academia over the years, in particular describing the path from my early work on branch prediction to the state of the art today. I will end by discussing our future work in this area.