The Need for Fine-Pitch 3D IC Die Bonding Technology: Power Performance Benefits PerspectiveSpeaker: Sung Kyu Lim – Suwanee, GA, United States
Topic(s): Architecture, Embedded Systems and Electronics, Robotics
AbstractSome of the most popular technologies being actively adopted by the semiconductor industry for 3D heterogenous integration are micro-bumping and hybrid bonding. In this talk, we quantify and compare the power, performance, and area (PPA) of 3D ICs built with these two bonding technologies. We use the pitch values that represent the current and the future of these options. Our studies are based on commercial quality full-chip GDS layouts and sign-off PPA analysis of commercial processor architectures designed with commercial process development kits (PDK). We analyze the impact of 3D interconnects enabled by micro-bumps and hybrid bond pads at various pitches on full-chip critical path delay, memory latency, and power consumption. In addition, we investigate the power delivery and thermal issues in these bonding technologies and develop solutions to mitigate the associated reliability issues. We also describe the commercial-quality RTL-to-GDS tools developed to enable these studies.
About this LectureNumber of Slides: 40
Duration: 60 minutes
Languages Available: English
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