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In this talk, we quantify and compare the power, performance, and area (PPA) of 3D ICs built with these two bonding technologies. We use the pitch values that represent the current and the future of these options. Our studies are based on commercial quality full-chip GDS layouts and sign-off PPA analysis of commercial processor architectures designed with commercial process development kits (PDK). We analyze the impact of 3D interconnects enabled by micro-bumps and hybrid bond pads at various pitches on full-chip critical path delay, memory latency, and power consumption. In addition, we investigate the power delivery and thermal issues in these bonding technologies and develop solutions to mitigate the associated reliability issues. We also describe the commercial-quality RTL-to-GDS tools developed to enable these studies. </div> <div class="row lecture__section"> <h2>About this Lecture</h2> <span> <strong>Number of Slides: </strong> 40</span><br/> <span> <strong>Duration: </strong> 60 minutes </span><br/> <span> <strong>Languages Available: </strong> English</span><br/> <span> <strong>Last Updated: </strong> <span id="lecDate"></span> </span> </div> <div class="row lecture__section"> <h2>Request this Lecture</h2> <p>To request this particular lecture, please complete this <a href="https://services.acm.org/public/speakers/request_lecture.cfm?lecture_id=14945" target="_blank">online form.</a> </p> </div> <div class="row lecture__section"> <h2>Request a Tour</h2> <p>To request a tour with this speaker, please complete this <a href="https://services.acm.org/public/speakers/request_tour.cfm?lecturer_id=16109" target="_blank">online form.</a> </p> <p>All requests will be sent to ACM headquarters for review.</p> </div> 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