Test Challenges and Solutions for Resilient Non-Volatile Memory Design

At the end of Silicon roadmap, several emerging non-volatile memory (NVM) technologies have surfaced. Due to plentitude of features such as, non-volatility, capability to create new computation paradigms, scalability and low-power, these NVMs have created substantial excitement in the design community. This talk will uncover the test challenges associated with some of these promising technologies such as, Spin-Transfer Torque RAM (STTRAM) and Resistive RAM (ReRAM) that can be harmful for the yield. This is specifically true in high-volume manufacturing of large capacity NVM arrays. Simulation and experimental data will be used to demonstrate NVM's sensitivity to magnetic field and temperature as potential sources of integrity loss. Role of test in assuring high degree of resiliency and memory integrity will also be discussed.