Memory hierarchies in modern processorsSpeaker: Per Stenstrom – Gothenburg, Sweden
Topic(s): Hardware, Power and Energy , Architecture, Embedded Systems and Electronics, Robotics
The compute landscape is moving towards being data centric rather than compute centric as in the past. This puts lots of pressure on the memory system in modern computers. This lecture reviews design principles of memory hierarchies in modern processors. It provides an overview of memory technologies that are being used and are emerging. It provides an in-depth coverage of principles of multi-level cache hierarchies including inclusion/non-inclusion, insertion/eviction policies, and prefetching. It also covers principles for cache coherence maintenance.
About this LectureNumber of Slides: 25
Duration: 45 minutes
Languages Available: English
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