Bio:
Per Stenstrom is a professor of computer engineering at Chalmers University of Technology. His research interests are in computer architecture. He has authored or co-authored four textbooks and about 200 publications and 20 patents in this area. He is known for his many contributions to high-performance memory systems which has awarded him a Fellow of the ACM and the IEEE. He has extensive experience in scientific publishing as editor-in-chief and program chair of prestigious scientific journals and conferences. Apart from acting as the associate editor-in-chief of JPDC in the architecture area, he acts as senior associate editor of ACM TACO and topical editor of IEEE Transactions on Computers. He has been program chair or co-chair of the IEEE/ACM Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, the IEEE Parallel and Distributed Processing Symposium and ACM International Conference on Supercomputing. He is a member of the Royal Swedish Academy of Engineering Sciences, Academia Europaea and the Royal Spanish Academy of Engineering Science.
Available Lectures
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Compression in the memory hierarchy
The compute landscape is moving towards being data centric rather than compute centric as in the past. It is well known that cache and memory capacity has a significant impact on...
- Databound computer architectures
There are two trends that will have a significant impact on how to sustain an exponential computational performance growth at a reduced power consumption in the future. One trend is that...- Memory consistency models
The compute landscape is moving towards being data centric rather than compute centric as in the past. This puts lots of pressure on the memory system in modern computers and optimizations...- Memory hierarchies in modern processors
The compute landscape is moving towards being data centric rather than compute centric as in the past. This puts lots of pressure on the memory system in modern computers. This lecture...- Microarchitectures of modern processors
Exploiting parallelism at all levels of the compute stack is a prerequisite for delivering high compute performance. This ranges from instruction-level parallelism (ILP) to program or...To request a tour with this speaker, please complete this online form.
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- Databound computer architectures