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This ranges from instruction-level parallelism (ILP) to program or thread-level parallelism (TLP). ILP has been a key enabler for high single-thread compute performance. This lecture focuses on that. </div> <div> <br /> </div> <div> This lecture provides an overview of the microarchitecture of modern processors. It starts out with the challenges related to instruction pipelining (hazards and exception handling). It then focuses on concepts for ILP exploitation including out-of-order instruction execution covering concepts such as the Tomasulo algorithm, branch prediction, speculation and multithreaded execution. </div> <div> <br /> </div> </div> <div class="row lecture__section"> <h2>About this Lecture</h2> <span> <strong>Number of Slides: </strong> 25</span><br/> <span> <strong>Duration: </strong> 45 minutes </span><br/> <span> <strong>Languages Available: </strong> English</span><br/> <span> <strong>Last Updated: </strong> <span id="lecDate"></span> </span> </div> <div class="row lecture__section"> <h2>Request this Lecture</h2> <p>To request this particular lecture, please complete this <a href="https://services.acm.org/public/speakers/request_lecture.cfm?lecture_id=15451" target="_blank">online form.</a> </p> </div> <div class="row lecture__section"> <h2>Request a Tour</h2> <p>To request a tour with this speaker, please complete this <a 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